Introduction:
The proliferation of wireless products over past few years has been rapidly increasing. New wireless standards such as GPRS and HSCSD have brought new challenges to wireless transceiver design. One pivotal component of transceiver is frequency synthesizer.
Two major requirements in mobile applications are efficient utilization of frequency spectrum by narrowing the channel spacing and fast switching for high data rates. This can be achieved by using fractional- N PLL architecture. They are capable of synthesizing frequencies at channel spacings less than reference frequency. This will increase the reference frequency and also reduces the PLL's lock time.
The proliferation of wireless products over past few years has been rapidly increasing. New wireless standards such as GPRS and HSCSD have brought new challenges to wireless transceiver design. One pivotal component of transceiver is frequency synthesizer.
Two major requirements in mobile applications are efficient utilization of frequency spectrum by narrowing the channel spacing and fast switching for high data rates. This can be achieved by using fractional- N PLL architecture. They are capable of synthesizing frequencies at channel spacings less than reference frequency. This will increase the reference frequency and also reduces the PLL's lock time.
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